Publication

Abstract : An efficient scan & ATPG technique for reducing the power consumed in the test mode is suggested in this paper. The reduction in power is achieved by reducing the switching activity during the shift operation in circuit under test . This suggested approach is based on stitching the scan cells with similar weight for logic 1 and 0's in to the same scan chain. Experiments done on ISCAS89 benchmark circuits reveled that the proposed method can achieve an average of 15% reduction in power, an average of 13% reduction in test time and an average of 29% reduction in energy with out degrading the fault coverage, performance and area.