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Virtual Channel and Switch Traversal in parallel to improve the latency in Network on Chip

Publication Type : Conference Paper

Publisher : 2020 2nd PhD Colloquium on Ethically Driven Innovation and Technology for Society (PhD EDITS)

Source : 2020 2nd PhD Colloquium on Ethically Driven Innovation and Technology for Society (PhD EDITS), IEEE, Bangalore, India (2020)

Url : https://ieeexplore.ieee.org/document/9315315

Campus : Bengaluru

School : School of Engineering

Department : Electronics and Communication

Year : 2020

Abstract : Network on Chip (NoC) connects multiple cores on a single chip. Traditionally input queued routers were used to arrange packets in a fixed order in a Virtual Channel (VC). This leads to Head of Line (HoL) blocking and increased latency. To address this issue, a VC router architecture is proposed which minimizes the total number of pipeline stages and uses a special buffer to avoid HoL blocking. The design is implemented using Booksim and the results show improved latency over conventional router

Cite this Research Publication : M. Katta and Dr. T. K. Ramesh, “Virtual Channel and Switch Traversal in parallel to improve the latency in Network on Chip”, in 2020 2nd PhD Colloquium on Ethically Driven Innovation and Technology for Society (PhD EDITS), Bangalore, India, 2020.

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