Back close

Verilog implementation of low density parity check codes

Publication Type : Journal Article

Publisher : International Journal of Applied Engineering Research

Source : International Journal of Applied Engineering Research, Research India Publications, Volume 10, Number 55, p.630-633 (2015)

Url : http://www.scopus.com/inward/record.url?eid=2-s2.0-84942311359&partnerID=40&md5=0c9dfaa7a962d1843a21f1351ddef62c

Campus : Amritapuri

School : School of Engineering

Department : Electronics and Communication

Year : 2015

Abstract : Low Density Parity Check Codes (LDPC) are forward error correcting codes that is used for transmission of messages over noisy communication channel. These are linear error correcting code and finding application in highly efficient transfer of messages over noisy channel. LDPC codes are usually defined by sparse parity check matrix which is usually randomly generated. LDPC codes are capable of performing close to Shannon capacity. The major uses of LDPC codes are in digital video broadcasting (DVB) standard and are being seriously considered in various real-life, magnetic storage, 10 Gb Ethernet, and high-throughput wireless local area network. In this Paper LDPC encoder and decoder architecture will be designed using verilog code. The algorithm that is used here is hard decision decoding algorithm. © Research India Publications.

Cite this Research Publication : D. Jose and Senthil Murugan, “Verilog implementation of low density parity check codes”, International Journal of Applied Engineering Research, vol. 10, pp. 630-633, 2015.

Admissions Apply Now