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Publication Type : Journal Article
Publisher : Journal of Microelectronics, Electronic Components and Materials (SCIE/Scopus)
Source : Journal of Microelectronics, Electronic Components and Materials (SCIE/Scopus), Volume 51, Issue 2, p.112 (2021)
Url : http://ojs.midem-drustvo.si/index.php/InfMIDEM/article/view/101
Keywords : Rise/Fall time; Processor Clock; CMOS process technology, vector-controlled circuit design; variable delay cell
Campus : Amritapuri
School : Department of Computer Science and Engineering, School of Engineering
Department : Computer Science
Year : 2021
Abstract : In the design of modern processor chips, proper clock distribution is a very important aspect which impacts the chip performance. It is the active cell of delay circuits and cells with variable delay that have the major involvement in clock distribution, thereby deciding the time slacks of all functionalities inside the chip as they help in proper input to output signal transmission with the adjustment of variable timing delays and monitor the output signal to have equal rise/fall time, which most of the existing delay elements fail to deliver. Therefore in this article, we have proposed an input vector based design that operates variable delay with balanced rise time and fall time for the output signal. We have also estimated the delay and output voltage in terms of a mathematical model. This new configuration is executed across the commercial platform of Cadence Virtuoso® using 90nm technology node and by taking 1GHz input signal and power supply 1.1V. The execution outcome confirms the desired features of our proposed design are correctly upheld under typical conditions and even in process corner variations.
Cite this Research Publication : Dr. Pritam Bhattacharjee, Bidyut K. Bhattacharyya, and Alak Majumder, “Vector Controlled Delay Cell with Nearly Identical Rise/Fall Time for Processor Clock Application”, Journal of Microelectronics, Electronic Components and Materials (SCIE/Scopus), vol. 51, no. 2, p. 112, 2021.