Publication

Abstract : Power dissipation of a VLSI chip was not a concern in the past. A lot of effort has been put into synthesis for speed and area, power optimization has been explored only recently. Since power estimation is the foremost step in any low power design; this work concentrates on developing a technique that estimates the toggle rates for circuits implemented on a 4-input LUT based FPGA using probabilistic technique. The aim of this work is to develop a toggle rate estimation technique with improved accuracy by incorporating the effects of correlation of logic signals and glitches. This approach is tested on a set of MCNC circuits. The ABC logic synthesis system is used for LUT mapping./p