Publication Type : Conference Paper
Publisher : NASA/ESA Conference on Adaptive Hardware and Systems, 2009. AHS 2009.
Source : NASA/ESA Conference on Adaptive Hardware and Systems, 2009. AHS 2009. , IEEE, San Francisco, CA (2009)
ISBN : 9780769537146
Accession Number : 10966769
Campus : Bengaluru
School : School of Engineering
Department : Computer Science
Year : 2009
Abstract : A dynamically reconfigurable on-chip multiprocessor architecture is presented, which can be adapted to changing application demands and to faults detected at run-time. The scalable architecture comprises lightweight embedded RISC processors that are interconnected by a hierarchical network-on-chip (NoC). Reconfigurability is integrated into the processors as well as into the NoC with minimal area and performance overhead. Adaptability of the architecture relies on a self-optimizing reconfiguration of the MPSoC at run-time. The resource-efficiency of the proposed architecture is analyzed based on FPGA and ASIC prototypes.
Cite this Research Publication : M. Porrmann, Dr. Madhura Purnaprajna, and Puttmann, C., “Self-optimization of mpsocs targeting resource efficiency and fault tolerance”, in NASA/ESA Conference on Adaptive Hardware and Systems, 2009. AHS 2009. , San Francisco, CA, 2009.