Publication

Abstract : .. The results obtained using MATLAB R2010a operating on HP 64-bit Intel i5 processor with clock speed of 2.53 GHz, are compared with HSPICE using the W-element model. The typical interconnect parameters [24] for simulations of single RLC interconnect and H-tree is given in Table 1 Tables 2 and 3 give the comparisons of 50 % delay values obtained using existing Eudes model [8], proposed models and HSPICE for various lengths, ramp input rise times, source resistances, parasitic capacitances, and load capacitances. These tables also include the error percentages of 50 % delays with respect to HSPICE results, which are measured from time domain responses of the existing model and proposed Table 3 indicate that, for H-tree 4th node the proposed MPTA-based model has worst case50 % delay error of 5.73 %, while the proposed MPTA-based model with S & S method has an error of 3.94 %. ...