Publication

Abstract : The increasing number of cores in embedded devices results in improved performance compared to single-core systems. Further, the unique characteristics of these systems provide numerous opportunities for power management which require models for power estimation. In this work, a statistical approach that models the impact of the individual cores and memory hierarchy on overall power consumed by Chip Multiprocessors is developed using Performance Counters. In particular, we construct a per-core based power model using SPLASH2 benchmarks by leveraging concurrency for multicore systems. Our model is simple and technology independent and as a result executes faster incurring lesser overhead. Evaluation of the model shows a strong correlation between core-level activity and power consumption and that the model predicts power consumption for newer observations with minimal errors. In addition, we discuss a few applications where the model can be utilized towards estimating power consumption.