Publication

Abstract : The power consumption of the integrated circuits have become increasingly a central topic of today's research. The need for low power has caused a major paradigm shift where power dissipation has become as important as performance and area. In this paper the original direct mapped cache of Alpha AXP 21064 processor is modified into set associative and phased set associative caches. The experimental results show that phased set associative cache is more power efficient than set associative cache. These three designs namely direct mapped, set associative and phased set associative caches are modeled using Verilog HDL, simulated in Modelsim and synthesized in Xilinx ISE 10.1. The power estimation and analysis is done using Xilinx XPower Analyser.