Publication Type : Conference Paper
Publisher : ICCTD 2009 - 2009 International Conference on Computer Technology and Development
Source : ICCTD 2009 - 2009 International Conference on Computer Technology and Development, Volume 1, Kota Kinabalu, p.530-534 (2009)
ISBN : 9780769538921
Keywords : Binary format, Cosine values, Data elements, DCT/IDCT, Field programmable gate arrays (FPGA), Hardware, Hardware implementations, Input datas, Low Power, Low power implementation, MATLAB, Modelsim, Optimum method, Pipelined implementation, Signal processing, Speed, Speed-ups, Verilog HDL, Xilinx FPGA
Campus : Amritapuri
School : School of Engineering
Center : Humanitarian Technology (HuT) Labs
Department : Electronics and Communication
Year : 2009
Abstract :
DCT/IDCT finds potent application in the field of image and signal processing. In this paper we concentrate on a novel five stage pipelined implementation, which consumes less power. The design uses Verilog HDL and is simulated in Modelsim 6.3b. Matlab is used to generate the data in binary format which serves as the input data and cosine values for computing 1D DCT/IDCT in HDL. There are other low power implementations as in [4], but in this novel implementation we prove that a lower power implementation can be done which also increases speed (of what?) by approximately five times over that of conventional implementations. The implementation of both non-pipelined (conventional) and pipelined method uses Xilinx XC3S4000 FPGA. The DCT/IDCT is found using the most common and optimum method of taking inputs as set of eight data elements [1], [2]. Finally, a comparison of the speeds of both implementations is made, and the speed up achieved by the low power pipelined implementation of 1D-DCT/IDCT is presented. © 2009 IEEE.
Cite this Research Publication : Rajesh Kannan Megalingam, Vineeth, S. V., Venkat, K. B., Mithun, M., and Srikumar, R., “Novel Low Power, High Speed Hardware Implementation of 1D DCT/IDCT Using Xilinx FPGA”, in ICCTD 2009 - 2009 International Conference on Computer Technology and Development, Kota Kinabalu, 2009, vol. 1, pp. 530-534