Publication

Abstract : Memory which is used for searching applications, like Network routers, operating at a higher speed is called Ternary Content Addressable Memory (TCAM). The requirement of TCAM is gradually growing in the searching field applications. TCAM memories are usually built in ASIC (Application Specific Integrated Circuit) which offers searching operation at a higher speed in a predetermined time but is expensive in cost. TCAMs designed on FPGAs (Field Programmable Gate Array) experience high power consumption, larger use of FPGA resources, and suffer from the inefficiency of storage. TCAM using multipumping and multiported SRAM is designed for achieving an effectual use of FPGA resources, and a reduction in usage of power and area. In the present SRAM based TCAM designs, there is an exponential growth in memory usage due to the increase in the patterns of TCAM, which is reduced by cascading the multiple blocks of SRAM (BRAMs) in FPGA that makes growth linear. BRAMs of FPGAs have restrictions in depth, which restricts the effectual storage of TCAM bits. In this paper, a modified TCAM design is proposed which avoids this restriction by using shallow sub-blocking of BRAMs. The design proposed in this paper operates the multiported SRAM by using the dual-port BRAM and by clocking it internally at a higher frequency using multipumping technique which allows access of the BRAM subblocks in one cycle of the system clock. These modifications in the divisional traditional TCAM table results in an effectual design of TCAM memory. The proposed design is coded in Verilog and simulated using the Xilinx ISE tool and was implemented on a Virtex 7xc7vx485 FPGA device. The proposed design has better performance, in terms of 26% reduction in power and 7% reduction in area, as compared to existing SRAM based TCAM design.