Publication

Abstract : In this paper, an area-efficient multi-transform architecture supporting transforms used in most popular video codecs like High Efficiency Video Coding (HEVC) and Advance Video Coding (AVC) is proposed. An eight-point integer DCT is implemented using two four-point integer DCTs. A three-stage pipelined and parallel multiplier-less architecture is designed using shift and add method. Proposed 1D DCT architecture uses 50% less resources as compared to other approach in literature and is capable of producing eight outputs for every clock cycles after the initial latency. Architecture is scalable to 2D DCT, and higher order DCTs can be computed either by reusing 1D structure or by duplicating the 1D structure. Proposed 1D and 2D DCT structures are simulated using Xilinx ISE and MATLAB tools and validated for the results. Further, the design is synthesized on Virtex-6 FPGA board and consumes 38% less area when compared with the standalone architectures. Proposed structure is found to be efficient in terms of resource utilization while comparing with architectures reported in literature.