Publication Type : Journal Article
Publisher : J. of Information and Computing Science
Source : J. of Information and Computing Science, Volume 2, Number 1, p.66–70 (2007)
Keywords : Circuit Partition and Delay minimization., Graph Partition
Campus : Coimbatore
School : School of Engineering
Department : Mathematics
Year : 2007
Abstract : Sequential graph partitioning algorithms have been developed to fulfill the requirements of emerging multi-phase problems in circuit delay models. In this paper we propose a heuristic algorithm for kpartition, which minimizes the circuit delay and cut size. Experimental results with MCNC benchmark circuits have shown that the delay in the circuit can be reduced by marginally in comparison with the other algorithms
Cite this Research Publication : Dr. Somasundaram K., “Multi-level Sequential circuit partitioning for delay minimization of VLSI circuits”, J. of Information and Computing Science, vol. 2, pp. 66–70, 2007.