Publication

Abstract : The semiconductor industry is expanding swiftly and the demand for memory and faster access of memory is increasing. The data stability and energy usage are the basic requirements of cache memory in embedded processors that uses SRAM. The SRAM cell parameters that require scrutiny at lower supply voltages are data stability, leakage current and delay. In order to ameliorate the stability further and lower the substrate (junction) leakage current in comparison to the existing SRAM cells, the MTCMOS ST SRAM cell is introduced in this paper. The proposed MTCMOS ST SRAM cell uses HVT and LVT MOSFETs that helps in reduction of the average power consumption by subsiding the leakage current. The proposed MTCMOS ST SRAM cell is implemented, analysed, verified and compared to the existing SRAM cells using Cadence Virtuoso with a channel length of 45 nm at a power supply of 500 mV. In proposed MTCMOS ST SRAM cell, i) read stability RSVNM is increased by 5.89%, 5.72% and 4.74% ii) write stability WTV is increased by 4.16%, 4.16% and 5.05% iii) hold stability HSNM is increased by 0.24% iv) power consumption is decreased by 58.87%, 3.164% and 66.49% in comparison to conventional 6T, existing 8T and existing 9T SRAM cell respectively v) overall read path leakage current is reduced by 94.83% and 87.420%, when compared with existing 8T and existing 9T SRAM cell respectively.