Publication

Abstract : The factors which play a pivotal role in VLSI system design are power, delay and area. In order to carry out fast arithmetic functions in many data processing processors, Carry Select Adders (CSLAs) are widely used because they are one amongst many of the fast adders that could be used for the high speed data processing. CSLAs stand out from the remaining conventional adders in terms of performing faster operations. The scope for reduction in area can be observed from the structure of CSLA. Hence a gate level modification has been proposed for the regular CSLA. Based on this modification 16-b, 32-b, 64-b and 128-b SQRT CSLA has been designed. Parameters such as area, power and delay have been analyzed and compared with the regular SQRT CSLA. The comparison between regular and modified CSLA showed a reduction in area and power. This work proposes the use of simple, optimized and an efficient gate-level modification to significantly reduce the area and power of carry select adder with a slight increase in delay.