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Methods for reduced trench isolation step height

Publication Type : Patents

Authors : Prof. Krishnashree Achuthan, K. Sahota

Source : (2003)

Url : http://www.google.com/patents/US6613646

Campus : Amritapuri

School : Centre for Cybersecurity Systems and Networks, School of Engineering

Center : Cyber Security, TBI

Department : cyber Security

Year : 2003

Abstract : pShallow trench isolation techniques are disclosed in which a thin nitride layer is formed on a semiconductor substrate, and a trench is formed through the nitride layer and into the semiconductor substrate, which is then filled. The wafer is then planarized using a fixed-abrasive CMP process to mitigate or avoid step height in the shallow trench isolation process. The nitride layer is then removed following planarization/p

Cite this Research Publication : K. Sahota and Dr. Krishnashree Achuthan, “Methods for reduced trench isolation step height”, 2003

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