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Method of manufacturing a seed layer with annealed region for integrated circuit interconnects

Publication Type : Patents

Publisher : Volume US6649511 B1, Number US 10/272,760

Authors : Prof. Krishnashree Achuthan, Marathe, A. P.

Source : U.S. Patent US 10/272,7602003

Url : http://www.google.com/patents/US6649511

Campus : Amritapuri

School : Centre for Cybersecurity Systems and Networks, School of Engineering

Center : Cyber Security, TBI

Department : cyber Security

Year : 2003

Abstract : pA manufacturing method provides a semiconductor substrate with a semiconductor device. A dielectric layer is formed on the semiconductor substrate and an opening provided therein. An barrier layer lines the opening and a seed layer is deposited to line the barrier layer. A conductor core fills the opening over the barrier layer to form a conductor channel. The seed layer is annealed to form an annealed region, which securely bonds the seed layer to the barrier layer and prevents electromigration along the surface between the seed and barrier layers./p

Cite this Research Publication : Dr. Krishnashree Achuthan and Marathe, A. P., “Method of manufacturing a seed layer with annealed region for integrated circuit interconnects”, U.S. Patent US 10/272,7602003

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