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Method for semiconductor wafer planarization by isolation material growth

Publication Type : Patents

Publisher : Volume US7052969 B1, Number US 10/190,002

Authors : Prof. Krishnashree Achuthan, K. S. Sahota

Source : U.S. Patent US 10/190,0022006

Url : http://www.google.com/patents/US7052969(link is external)

Campus : Amritapuri

School : Centre for Cybersecurity Systems and Networks, School of Engineering

Center : Cyber Security, TBI

Department : cyber Security

Year : 2006

Abstract : pA method of manufacturing a planarized semiconductor wafer in which a semiconductor wafer is provided with a chemical-mechanical polishing stop layer deposited thereon. A photoresist layer is processed and used to form a patterned chemical-mechanical polishing stop layer and shallow trenches. A shallow trench isolation material is then grown on the chemical-mechanical polishing stop layer and in the shallow trenches, and is chemical-mechanical polished to the chemical-mechanical polishing stop layer./p

Cite this Research Publication : K. S. Sahota and Dr. Krishnashree Achuthan, “Method for semiconductor wafer planarization by isolation material growth”, U.S. Patent US 10/190,0022006

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