Publication Type : Patents
Publisher : Number US 10/150,282 (2003)
Authors : Prof. Krishnashree Achuthan, J. D. Bhakta, Hui, A
Source : U.S. Patent US 10/150,2822003.
Url : http://www.google.com/patents/US6605517
Campus : Amritapuri
School : Centre for Cybersecurity Systems and Networks, School of Engineering
Center : Cyber Security, TBI
Department : cyber Security
Year : 2003
Abstract : pA method for reducing nitride residue from a silicon wafer during semiconductor fabrication. The wafer includes a nitride mask defining active regions and isolation regions wherein the isolation regions are formed by trenches. The method includes providing an optimized oxide deposition process in which a temperature gradient of a CVD chamber is improved by performing the following steps. First, at least one silicon wafer is placed into the chamber on a quartz boat having an increased slot size, preferably at least 6 mm. Second, the quartz boat is centered in approximately a center of the chamber so that the wafer is located in a center section of the chamber to avoid the temperature gradient at the ends of the chamber, such that when oxide gas is injected onto the wafer, an oxide layer having a substantially uniform thickness is formed on the wafer. The method further includes performing an optimized polishing process on the oxide wherein the oxide is polished down to approximately a level of the nitride, but where more of the oxide is removed from the edge area of the wafer than in the center area. Thereafter, the nitride is stripped from the wafer, wherein substantially all of the nitride is removed from the wafer, thereby minimizing nitride residue./p
Cite this Research Publication : J. D. Bhakta, Dr. Krishnashree Achuthan, and Hui, A., “Method for minimizing nitride residue on a silicon wafer”, U.S. Patent US 10/150,2822003.