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Method for decreasing sheet resistivity variations of an interconnect metal layer

Publication Type : Patents

Publisher : U.S. Patent US 11/388,3902008

Authors : Prof. Krishnashree Achuthan, Davis, B., Sahota, K., and Xie, J.

Source : U.S. Patent US 11/388,3902008

Campus : Amritapuri

School : Centre for Cybersecurity Systems and Networks, School of Engineering

Center : TBI

Department : cyber Security

Year : 2008

Abstract : pAccording to one exemplary embodiment, a method includes a step of forming a number of trenches in a dielectric layer, where the dielectric layer is situated over a wafer. The method further includes forming a metal layer over the dielectric layer and in the trenches such that the metal layer has a dome-shaped profile over the wafer. The method further includes performing a planarizing process to form a number of interconnect lines, where each of the interconnect lines is situated in one of the trenches. The dome-shaped profile of the metal layer causes the interconnect lines to have a reduced thickness variation across the wafer after performing the planarizing process. The interconnect lines are situated in an interconnect metal layer, where the dome-shaped profile of the metal layer causes the interconnect metal layer to have increased sheet resistivity uniformity across the wafer after performing the planarizing process./p

Cite this Research Publication : Dr. Krishnashree Achuthan, Davis, B., Sahota, K., and Xie, J., “Method for decreasing sheet resistivity variations of an interconnect metal layer”, U.S. Patent US 11/388,3902008

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