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Method for controlling poly 1 thickness and uniformity in a memory array fabrication process

Publication Type : Patents

Publisher : Volume US7294573 B1, Number US 11/035,188

Authors : Prof. Krishnashree Achuthan, Kim, U., Regalado, P. C., and Sahota, K

Source : U.S. Patent US 11/035,1882007

Url : http://www.google.com/patents/US7294573

Campus : Amritapuri

School : Centre for Cybersecurity Systems and Networks, School of Engineering

Center : Cyber Security, TBI

Department : cyber Security

Year : 2007

Abstract : pAccording to one exemplary embodiment, a method includes planarizing a layer of polysilicon situated over field oxide regions on a substrate to form polysilicon segments, where the polysilicon segments have top surfaces that are substantially planar with top surfaces of the field oxide regions, and where the field oxide regions have a first height and the polysilicon segments have a first thickness. The method further includes removing a hard mask over a peripheral region of the substrate. According to this exemplary embodiment, the method further includes etching the polysilicon segments to cause the polysilicon segments to have a second thickness, which causes the top surfaces of the polysilicon segments to be situated below the top surfaces of the field oxide regions. The polysilicon segments can be etched by using a wet etch process. The polysilicon segments are situated in a core region of the substrate./p

Cite this Research Publication : Dr. Krishnashree Achuthan, Kim, U., Regalado, P. C., and Sahota, K., “Method for controlling poly 1 thickness and uniformity in a memory array fabrication process”, U.S. Patent US 11/035,1882007

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