Publication

Abstract : In contemporary times, one of the most crucial requirements for digital signal processing is high power efficiency. Realizing different multimedia applications, such as processing images and videos, requires digital signal processing. Multipliers are widely utilized and considered to be one of the most important arithmetic logic units. It is also among the units which utilizes the most power in image processing applications. When precise processing is not necessary, approximate computing is an appealing technique to achieve major boosts in area, power, and speed in error-resistant applications. The purpose of this work is to present a unique approximate multiplier design that preserves accuracy metrics while consuming less power. This can serve as a helpful stand-in for precise multipliers. The effectiveness of this multiplier is evaluated based on its power consumption, error metrics, and image processing application performance. The simulation results demonstrate the effectiveness of the proposed architecture by showing reductions in power consumption of 28.1% and 45.5%, respectively, when compared to the existing approximate and exact multipliers. It also shows comparatively lower values of Normalized mean error distance (NMED) and Mean relative error distance (MRED) proving its efficacy.