Publication

Abstract : In this era of ever blooming technology, devices are developed to be more compatible and handy for the usage of people. Diminishing on-chip power has been the major concern in this nanotechnology period. Very-large-scale integration (VLSI) is the practice of developing an integrated circuit by combining several hundreds of transistors or other devices in a single chip. VLSI allows numerous functions to be added on in a single chip. Each process has inherently higher dynamic and leakage currents. Power dissipation of devices is the main concern when it applies to portable devices. Having high on-chip power degrades the devices reliability and its lifetime. There are various methods of reducing power usage by employing different algorithms, architectures, circuit logics and technology like threshold reduction. This work presents a cubic architecture designed using Vedic sutras from Vedic mathematics. It is compared with conventional architecture. Square of a binary number can be determined by using Dwanda yoga sutra of Vedic mathematics. It focuses at low power design of the architecture. This work shows that the proposed architecture has 21.53% and 46.56 % decrease in area and power respectively.