Publication Type : Conference Paper
Publisher : 2016 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS) (Scopus), IEEE
Source : 2016 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS) (Scopus), IEEE, Gwalior, India, p.250–254 (2016)
Url : https://ieeexplore.ieee.org/abstract/document/7829562
Keywords : Adders, chip size, clock gating technique, Clocks, D Flip Flop, double gated flip-flop, dynamic power flow, Finite state machine, finite state machines, flip-flops, gated clock approach, integrated circuit design, Latches, LECTOR, LECTOR based clock gating techniques, load flow, Logic gates, low power FSM design, low-power electronics, Power demand, Power dissipation, predictive technology model, sequential element, serial adder, size 32 nm, size 45 nm, size 65 nm, size 90 nm, Static Power, static power flow, Transistors
Campus : Amritapuri
School : Department of Computer Science and Engineering, School of Engineering
Department : Computer Science
Year : 2016
Abstract : As the chip size is getting decreased with the advent of technology, power dissipation has become a major issue to the circuit designers at the time of designing an integrated circuit. The substantial sources of power dissipation are the static power and dynamic power. A serial adder, one of the vital parts of any processor micro-architecture, is a victim to the huge power flow. In this paper, we have intervened on the solution for controlling both static and dynamic power flow by implementing the LECTOR based clock gating technique on the sequential elements of serial adder. LECTOR helps to reduce the static power by blocking the current between the power lines and gated clock minimizes the dynamic power by eliminating the needless switching of system clock. The simulation is carried out using 32nm, 45nm, 65nm and 90nm Predictive Technology Model and compared the result with Double Gated flip-flop based serial adder.
Cite this Research Publication : Dr. Pritam Bhattacharjee and Alak Majumder, “LECTOR Based Gated Clock Approach to Design Low Power FSM for Serial Adder”, in 2016 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS) (Scopus), Gwalior, India, 2016, pp. 250–254.