Publication Type : Journal Article
Publisher : Analog integrated circuits and signal processing
Source : Analog integrated circuits and signal processing. February 2017, DOI: 10.1007/s10470-017-0947-x.
Url : 10.1007/s10470-017-0947-x.
Campus : Chennai
School : School of Engineering
Center : Amrita Innovation & Research
Department : Electronics and Communication
Verified : Yes
Year : 2017
Abstract : This Paper focuses on improving the Harmonic Rejection Ratio (HRR) and the linearity of 3-Path 8-Phase harmonic rejection mixer with modified transconductance stage. The mixer core incorporates a feed-forward compensation technique in the transconductance stage for improving the linearity of the mixer with an Third order Input Intercept Point (IIP3) of 14 dBm. The Harmonic Rejection Mixer (HRM) using mixer cores with modified transconductance stage was designed using 90 nm CMOS process technology and the simulation results shows an improvement of IIP3 point of more than 25 dBm. A conversion gain of 12–4 dB was observed over the frequency range of 2.26–2.8 GHz (540 MHz bandwidth). Maximum third order HRR (\(HRR_3\)) of 45 dB and fifth order HRR (\(HRR_5\)) of 55 dB was observed on sweeping the RF power from −30 to 10 dBm. Deviations on the performance of the HRM was found to be very minimal on PVT variation.
Cite this Research Publication : Maran Ponnambalam, Mythily Kanaga, Premanand V. Chandramani, “Improving HRR and linearity in 3P-8P HRM using mixer with modified transconductance stage” Analog integrated circuits and signal processing. February 2017, DOI: 10.1007/s10470-017-0947-x.