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Implementation of Viterbi coder for text to speech synthesis

Publication Type : Conference Paper

Publisher : 2015 IEEE International Conference on Computational Intelligence and Computing Research (ICCIC)

Source : 2015 IEEE International Conference on Computational Intelligence and Computing Research (ICCIC), IEEE, Madurai, India (2015)

Url : https://ieeexplore.ieee.org/document/7435659

Campus : Bengaluru

School : School of Engineering

Department : Electronics and Communication

Year : 2015

Abstract : This paper talks about designing an efficient Viterbi coder which can be used for Text to Speech synthesis (TTS). Today numerous applications uses Text to Speech synthesis (TTS) and Viterbi coder plays a key role in producing the synthesized output. Viterbi algorithm includes numerous iterations to produce the output and hence power utilization is more. We propose a technique which uses a memory access technique along with pipelined precomputation to reduce the power utilization and makes a trade off with speed. Here the overall power consumed by memory is 17 mw less than that of the power consumed by circuit used in the system.

Cite this Research Publication : M. L. Padmesh and P. Sathish Kumar, “Implementation of Viterbi coder for text to speech synthesis”, in 2015 IEEE International Conference on Computational Intelligence and Computing Research (ICCIC), Madurai, India, 2015.

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