Publication

Abstract : For many DSP applications, specific processor performance is of major concern. Multiplication has an important role in the functions like Fast Fourier Transform (FFT) and Discrete Cosine Transform (DCT). One of the easiest ways to increase the speed of these functions is to improve the performance of the multiplier. This will, in turn, increase the total performance of the processor. In this paper, design of 6:3 and 7:3 binary compressors using 3-bit stacker circuit is proposed. The function of the 3-bit stacker is to group all the ”1” s together. The proposed 6:3 and the 7:3 compressor designs use two 3-bit stacker circuits. The compressors are designed with reduced number of XOR gates which improves the performance. The proposed compressors are used in the existing multiplier design and analysed for power and delay. Cadence RTL compiler is used for synthesizing these compressor designs. The proposed 7:3 and 6:3 compressors show 14% and 23% decrease in delay and 6% and 17% decrease in power respectively, when compared with the basic compressor designs which use full adders and half adders.