Publication

Abstract : Non-Binary Low-Density Parity-Check (NB-LDPC) codes surpass other binary codes when it comes to error-correction performance. The main drawback of NB-LDPC codes is high computational complexity especially when it comes to check node processing. The complexity further increases with increasing Galois Field (GF) order. The existing Basic-Set Trellis Min-Max algorithm-based NB-LDPC decoder over GF(4) which is a sequential design achieves a frequency of 136.14 MHz and throughput of 41.891 Mbps. In this paper, a (6,3) code based Basic-Set TMM NB-LDPC decoders over GF(4) with 2- and 6-parallelism are designed, simulated, synthesized, and implemented by using the Xilinx Vivado tool and the Virtex-7 FPGA. The decoder architectures with 2- and 6-parallel improve throughput up to 36.57% and 56.42% respectively compared with sequential implementation.