Publication

Abstract : In digital signal processing applications, the critical route includes the parallel summation of multiple operands. High compression ratio counters and compressors are required to speed up the summing operation. In the proposed work, (15,4) counters and (7,3) counters are designed, while the counters are sorted using the proposed sorting network. The counter's inputs are split asymmetrically into two groups and fed into sorting networks to produce reordered sequences that can only be represented by one-hot code sequences. The counters are constructed in Xilinx using Verilog and obtained the results of time and delay. This is then applied to the sorting network and checked the sorting network for counters (7,3) and (15,4). In addition to this, sorting network was made effective in sorting the larger numbers either in the ascending or in the descending order.