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Publication Type : Conference Paper
Publisher : 2017 IEEE International Conference on Computational Intelligence and Computing Research, ICCIC 2017
Source : 2017 IEEE International Conference on Computational Intelligence and Computing Research, ICCIC 2017, IEEE, Coimbatore, India (2017)
Url : https://ieeexplore.ieee.org/document/8524556
Campus : Bengaluru
School : School of Engineering
Department : Electronics and Communication
Year : 2017
Abstract : Traditional verification techniques using Verilog lack flexibility of reusable verification environment and faster time to market. The Universal Verification Methodology (UVM) Class Library provides the building blocks needed to develop reusable verification components and test environments using SystemVerilog. This paper focuses on developing a verification environment using SystemVerilog implementation of UVM for JTAG which will introduce an automated stimulus generating verification environment that checks the debugging functionality of JTAG for any given DUT. UVM based functional verification tries to achieve maximum functional coverage by adding constrained random test cases covering all possible scenarios. whereas, functional coverage model cannot be analyzed in traditional verification environment using Verilog. A functional coverage model is built here to find out whether the verification achieves the expected coverage or not. The coding is done using SystemVerilog and the simulation is done using Questasim.
Cite this Research Publication : C. Elakkiya, Dr. N.S. Murty, Babu, C., and Jalan, G., “Functional Coverage - Driven UVM Based JTAG Verification”, in 2017 IEEE International Conference on Computational Intelligence and Computing Research, ICCIC 2017, Coimbatore, India, 2017.