Publication

Abstract : Convolutional neural networks (CNNs) are commonly used in modern AI systems. These models feature millions of layer connections, which are memory- and computationally-intensive. Using these models on an embedded mobile application requires a lot of power and bandwidth to retrieve off-chip DRAM data. Reducing data transmission between on-chip and off-chip DRAM is key to high throughput and energy efficiency. The proposed FPGA-based hardware accelerator achieves these goals by employing a patch-wise design that uses less on-chip memory. The proposed architecture involves parallel computations on the patches stored in the on-chip memory. The proposed architecture is verified with a synthetic aperture radar (SAR) dataset, crucial in military surveillance, disaster management, and marine vigilance applications. The proposed accelerator prevented the need for a cloud-based server and was implemented on the Zynq ultra-scale ZCU104 FPGA board. The proposed architecture consumed 81% less power than GPU and 44% less than state-of-the-art works, underscoring its eco-friendliness. Furthermore, the proposed architecture achieved 24 GOP/s.