Publication

Abstract : Because of their excellent error correction performance, Low-Density Parity Check Codes (LDPC) have become the most widely used technique for forward error correction in almost all modern communications applications. This paper introduces an FPGA implementation of a partial parallel, flexible LDPC decoder based on the Min-Sum decoding algorithm. The suggested architecture uses a combination of unicast and multicast communications between its processing elements in order to reduce the intercommunication overhead and at the same time, keep the processing elements simple. The use of the less complex Min-Sum algorithm on the suggested architecture produces a very compact and resource efficient design which allows the instantiation of many processing elements to deliver high processing rate To allow flexibility to support different codes, a non-blocking interconnection network is used to pass messages between processing elements. It is a modified version of the multi stage network called Arbitrary Size Benes. The decoder architecture was implemented on Virtex5 FPGA using VHDL in Xilinx ISE environment. Results show efficient resources utilization compared to other implementations. The decoder achieves up to 3.49 Gbps per iteration for a code length of 2640 with BER of 10-5 at 4.4dB.