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Dual silicon layer for chemical mechanical polishing planarization

Publication Type : Patents

Authors : Prof. Krishnashree Achuthan, Ahmed, S. S., Wang, H. H., and Yu, B.

Source : (2004)

Url : http://www.google.com/patents/US6756643

Campus : Amritapuri

School : Centre for Cybersecurity Systems and Networks, School of Engineering

Center : Cyber Security, TBI

Department : cyber Security

Year : 2004

Abstract : pA FinFET-type semiconductor device includes a fin structure on which a relatively thin amorphous silicon layer and then an undoped polysilicon layer is formed. The semiconductor device may be planarized using a chemical mechanical polishing (CMP) in which the amorphous silicon layer acts as a stop layer to prevent damage to the fin structure./p

Cite this Research Publication :
Dr. Krishnashree Achuthan, Ahmed, S. S., Wang, H. H., and Yu, B., “Dual silicon layer for chemical mechanical polishing planarization”, 2004

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