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Differential pressure chemical-mechanical polishing in integrated circuit interconnects

Publication Type : Patents

Publisher : Volume US6426297 B1

Authors : Prof. Krishnashree Achuthan, K. S. Sahota, Lopatin, S. D

Source : Volume US6426297 B1 (2002)

Url : http://www.google.com/patents/US6426297

Campus : Amritapuri

School : Centre for Cybersecurity Systems and Networks, School of Engineering

Center : Cyber Security, TBI

Department : cyber Security

Year : 2002

Abstract : pA method is provided for manufacturing an integrated circuit having a semiconductor substrate with a semiconductor device. A dielectric layer is formed on the semiconductor wafer and an opening is formed in the dielectric layer. A barrier layer is deposited to line the opening and a conductor core is deposited to fill the channel opening over the barrier layer. The semiconductor wafer is then subjected to chemical-mechanical polishing using a differential pressure between the center of the semiconductor wafer and its periphery./p

Cite this Research Publication :
K. S. Sahota, Dr. Krishnashree Achuthan, and Lopatin, S. D., “Differential pressure chemical-mechanical polishing in integrated circuit interconnects”, 2002

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