Publication

Abstract : In recent years, serious concerns have been raised against the tampering of integrated circuits due to outsourcing of circuits for fabrication. It has led to the addition of malicious circuitry known as Hardware Trojan. In this paper, a transition probability based node reduction technique for faster and efficient Hardware Trojan (HT) detection has been attempted. In the proposed method, the fact that the least controllable and observable nodes or the nodes with least transition probability are more vulnerable as Trojan sites is taken into consideration. The nodes that have lesser activity than the threshold are the candidate nodes. At each candidate node, segmentation is done for further leakage power analysis to detect the presence of Trojans. Experimental results observed on ISCAS’85 and ISCAS’89 benchmark circuits illustrate that the proposed work can achieve remarkable node reduction upto 78.81% and time reduction upto 58.7%. It was also observed that the circuit activity can be increased by varying the input probability. Hence, for further reduction in the Trojan activation time, the weighted input probability was obtained.