Publication

Abstract : Technological innovation creates new challenges in terms of security, trust, and privacy. In today's society, when digital electronic gadgets predominate, their security is becoming as a key source of concern. In such cases, Physical Unclonable Functions (PUFs) have come to our support. PUF utilizes the manufacturing process differences in ICs or devices to provide unique responses. This one-of-a-kind reaction of an IC may be utilized in a variety of hardware security applications such as secret key creation, device authentication, and so on. The response response of an embedded PUF may be regarded as serving a unique identifier for that device. The most common PUF implementation technique field-programmable gate arrays (FPGAs). Due to its unclonable behavior, PUF’s demand is increasing day by day to identify and authenticate the devices. This research study focuses on performing a detailed analysis on various PUF architectures and to come up with an efficient architecture, which consumes less power and less area overhead. In regards to this a new PUF design named Double XOR- based Arbiter PUF has been proposed to improve the dynamic power consumption, area overhead along with higher uniqueness. The proposed design is also compared with other existing designs of Arbiter PUF, XOR PUF, Feed-Forward PUF and Feed-Forward XOR Arbiter PUF in terms of dynamic power consumption, resource utilization. The architectures are modeled using Verilog HDL language in Xilinx ISE software tool and implemented on Virtex 6 FPGA board. The proposed design achieves a power consumption improvement of approximately 7.5%, 13.5% and 16.4% for 4-bit, 8-bit and 16-bit CRP design respectively.