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Design and implementation of two stage 5-bit pipelined SAR ADC

Publication Type : Conference Paper

Publisher : 2014 International Conference on Communication and Signal Processing

Source : 2014 International Conference on Communication and Signal Processing (2014)

Url : https://ieeexplore.ieee.org/document/6949991/

Keywords : Analog-to-digital converter (ADC), analogue-digital conversion, cascaded SAR ADC, Clocks, CMOS, CMOS integrated circuits, Delays, integrated circuit design, Inverters, passive component elimination, pipelined SAR ADC, power utilization, size 90 nm, Software packages, successive approximation (SAR), Switching circuits

Campus : Bengaluru

School : School of Engineering

Department : Electronics and Communication

Verified : No

Year : 2014

Abstract : pA 250 MS/s cascaded two-stage 5-bit pipelined SAR ADC in 90nm CMOS was designed and validated. Elimination of passive components leads to an improvement in power utilization, improvement in speed and at the same time is not limited by process variations. The SAR ADC design was validated as a Matlab/Simulink macro model and verified in 90nm CMOS through Agilent ADS. Successive approximation for each stage is achieved through a binary search in a round robin mode that reduces the approximation time. DNL was observed to be 0.7 LSB./p

Cite this Research Publication : A. Padmanaban M., P. Maran, and Premanand Venkatesh Chandramani, “Design and implementation of two stage 5-bit pipelined SAR ADC”, in 2014 International Conference on Communication and Signal Processing, 2014.

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