Publication

Abstract : The importance of on-chip communication interconnects was greatly highlighted with the advent of semiconductor technology at nanoscale domain. As the sizes of semiconductor features are reduced day by day, there occurred problems related to wiring. Network-on-Chip architectures are therefore implemented to overcome the wiring issues and have lately been considered as an important area for research. The communication on NoC is carried out in specific topologies by means of routers. In this paper, Partial Mesh of Grid topology (PMG) is considered. We use the Quality of Service (QoS) mechanism to minimize the area and power. PMG-based NoC will give minimum area and power and it reduces the high chances of redundant connections. Throughput and latency are analysed along with other parameters like packet loss ratio and jitter using network simulator NS-2. Area and power analyses are done using Synopsys Design Compiler and PrimeTime PX tool. Our experimental results show that the architecture with QoS mechanism gives a significant reduction in area and power when compared to Region-based Routing (RBR) mechanism. Moreover, the partial mesh of grid topology gives minimal latency and high throughput when compared to mesh of grid topology. © Springer India 2016.