Publication

Abstract : In Deep Sub Micron (DSM) technology, the critical issues in the NoC interconnect design are to meet the performance, power consumption requirements of the SoC and to address reliability simultaneously, interconnect delay, power consumption and crosstalk noise. It is essential to select an optimal coding technique to improve communication reliability and reduce self and coupling switching activities. In this paper, Crosstalk Aware Transient Error Correction (CATEC) coding technique is proposed to handle the reliability issues and flit dependent switching activities. The achievable reliability and reduction of switching activities are evaluated using real-time traffics. It is proved that the CATEC technique corrects all the error patterns with one or two transient error bits and few error patterns with six to nine transient error bits. Furthermore, 99% of the error patterns with three, four and five transient error bits are too corrected for a 32 bit flit. This technique considerably reduces flit dependent self and coupling transitions. This results in low power NoC link and even avoids crosstalk to a greater extent.