Publication

Abstract : Power Supply Noise (PSN) in CPU cores or any integrated circuit (IC) chips is a problem of power line voltage degradation impelled due to the parasitic components (viz., resistance, capacitance and inductance) across the packaging. This lowers the operating frequency of the silicon chip during high volume manufacturing and thereby affects the overall performance. After numerous attempts to minimize the parasitic impacts of power delivery networks (PDN) in IC packages, researchers also started to look for circuital configurations that can curb down the coefficients of PSN (i.e., the instantaneous current i(t) and the current ramp di(t)dt during OFF to ON switching of packaged CPU/IC). Though variable frequency clock (VFC) has emerged as a potential solution, its design is found to be complex and power hungry. Hence, a novel and simple configuration of VFC embedded with leakage control transistor based clock gating (LCT-CG) is tendered in this article, where the pertaining circuits and integrated system have been designed using UMC 65nm CMOS with a supply of 1.1V. The performance of the design is tested on Master-Slave Flip-Flop (MSFF) and a few prominent benchmark circuits (viz., ISCAS’89 s27, s820, s832, s1196, s9234 and ITC’99 b02 and an IEEE 754 complaint single precision FPU) considering the PDN of existing CPU OLGA package. The system level validation of our proposed IC on A-Z80 CPU chip offers the average power and PSN to be mitigated by 30.06% and 42.63% against the conventional clocking.