Publication

Abstract : The main concept of the venture is Reducing the delay and area in VLSI architecture.the efficient VLSI architecture of interpolation filter for multistandard Digital Up Converter (DUC)is implemented by means of two step optimization technique is designed, such that area and delay is reduced. At first, the number of multiplication operation and addition operations are reduced using root-raised-cosine Finite Impulse Response filter for multistandard DUC. By using the constant multiplier number of addition operations are reduced. Shifting operations are performed while considering the constant multiplier. Multipliers are the basic element of any filter like FIR. Hence, a developed 2-bit (BCS) binary common sub-expression based elimination algorithm has been used for designing a constant multipliers. This technique has thrived in reducing the delay, area and power usage and improvement in operating frequency compared to the previously 3-bit BCS-based technique for designing the multi-standard DUC.