Publication

Abstract : System-on-Chip (SoC) design refers to integrating all components of a computer or other electronic system in to a single integrated circuit. Testing of System-on-chip (SoC) design is becoming a challenging job due to its inherent complexities and higher chip densities. We present a new testing technique to reduce the number of test pins available for test and hence to reduce the test cost. The paper introduces the concept of flexible width test architectures instead of fixed width test architectures. The paper analyzes fixed width and flexible width Test Bus Architecture (TBA) and Test Rail Architecture (TRA) possible for a sample SoC designs. Test strategy for all designs coded in Verilog or VHDL is implemented using Synopsys DFT Compiler and ATPG is run through Synopsys TetraMAX ATPG tool.