Publication

Abstract : The increasing requirement for portable devices has resulted in the evolution of techniques forimposing limits on the high power consumption. The operation of a VLSI system is greatly dependent on digitalmultiplication process through the multipliers. The multiplier design that is aging-aware has been utilized earlier.But, the negative bias temperature instability impact of pMOS transistor has led to the increase in the delay andlimited the speed of the multiplier. This resulted in the aging-aware 8-bit Booth multiplier being developed for betterthroughput and limited degradation in the performance. But in Booth multiplier, the number of partial products isgreater and results in the increase in the complexity for generating the product bits. Therefore, the aging-awaremultiplier design along with novel Adaptive Hold Logic (AHL) circuit is introduced in this work with the usage oflow power Vedic multiplier and modified Razor flip-flop. The Vedic multipliers have the capability of solving thehigh power dissipation issues and prevent the failures. Also, Vedic Multiplier possesses the benefits that with theincrease in the number of bits, gate delay and area rise very slowly in comparison with other multipliers. Hence itoffers efficiency with regard to time, space and power. Moreover, this architecture can be realized for × module bymaking use of ripple carry adder. The Vedic multiplier design is able to give the low power usage over the AHLcircuit and also it minimizes the timing violations. At last, the experimental results also show that the Vedicmultiplier with AHL circuit provides the low power and delay differentiated to the Column multiplier and Boothmultiplier.