Publication

Abstract : This paper presents the application of the Spurious Power Suppression Technique (SPST) on the Two-Speed Multiplier (TSM) that finds application in digital filters, artificial neural networks (ANN), and other machine learning algorithms. It is a radix-4, serial-parallel multiplier utilizing the concept of SPST to reduce the dynamic power by filtering out unwanted signal transitions in the arithmetic block. The control circuit of the multiplier dynamically skips addition operation for zero booth encodings and does computation only for non-zero booth encodings, thus making delay depends upon input bit pattern. This paper also discusses the merits and demerits of available Parallel Prefix Adders (PPAs) which can be used in the multiplier. Kogge Stone adder (KSA) with an improved prefix-computation stage to reduce the hardware complexity is used for Least Significant (LSP) and hybrid Han Carlson adder (HCA) with better area∗power is used for Most Significant (MSP) computations. TSM utilizes two sub-circuits with different critical paths which further improves the delay and throughput for a sub-set of inputs over the existing multipliers. The proposed SPST based modified TSM is implemented on an Intel Cyclone V 5CSEMA5F31A7 FPGA device and is evaluated against Booth serial, parallel-parallel and Serial-Parallel (SP) multipliers. Proposed SPST based TSM achieves 1.43x-1. 52x improvement in power-delay product and 1.096x-l.l3x improvement in area-power-delay product over the standard two-speed multiplier.