Publication Type : Conference Proceedings
Publisher : ICOEI
Source : 2019 3rd International Conference on Trends in Electronics and Informatics (ICOEI) (2019)
Url : https://ieeexplore.ieee.org/document/8862718
Keywords : Adders, area efficient floating-point four term fused dot product unit, carry increment adder(CIA_CLA), Conferences, Delays, digital signal processing applications, dot product operations, floating point arithmetic, floating-point operations, fused dot product, fused floating-point dot product unit, logical exponent, low power floating-point four term fused dot product unit, low-power electronics, Market research, merged floating-point scalar product unit, multiplying circuits, Power demand, single precision floating point multiplier, statistical applications, Table lookup, Vedic Mathematics, vedic multiplier, Vedic multiplier exponent
Campus : Coimbatore
School : School of Engineering
Department : Electronics and Communication
Year : 2019
Abstract : The four-term fused dot product (FDP) unit is designed for single precision floating-point by using the Vedic multiplier. The Dot product operations are frequently used in a graphics, statistical applications and Digital signal processing (DSP) applications. In this work, a low power and area efficient floating-point four term fused dot product unit is proposed by using Vedic mathematics. A merged floating-point scalar product unit uses Vedic multiplier, logical exponent of comparison and mantissa alignment, normalization, leading zero anticipation (LZA), compound addition and rounding to enhance the performance. The area and power are calculated to evaluate the proposed design. The proposed design is realized for a single precision floating point multiplier and synthesized with Vivado 2015.4.
Cite this Research Publication : D. L. Prasanna and Prabhu E., “An Efficient Fused Floating-Point Dot Product Unit Using Vedic Mathematics”, 2019 3rd International Conference on Trends in Electronics and Informatics (ICOEI). 2019.