Publication

Abstract : Design of electronic devices is very important to reduce power, delay and area of components because these factors are impact the quality and performance of devices. Adder is most fundamental and important device in microprocessors and DSP chips Carry Select Adder (CSA) is the finest adder of choice while considering the need for high speed arithmetic designs. Previous architectures i.e., Conventional CSA and Binary to Excess-1 Converter (BEC) based Square Root Carry Selected Adder (SQRT-CSA) clearly explained. The redundancies in logic operations and dependencies of data factors are effects the power, area and delay in any adder design. The analysis of BEC-based SQRT-CSA (BEC SQRT-CSA) clearly shows the possibility to reduce the power and area by proper modifications at gate-level architecture because this design has been effected by above factors. This work reduces the redundancy in logic operations by introducing a new adder instead of the conventional BEC. The proposed design generates the sum and carry signals for both carry input signals (Cin =0 and Cin =1) for n-number of bits using n-number of new adder. The proposed new adder implemented with less number of logic gates compared with Half Adder (HA). the proposed CSA has less power consumption of 1.5%,44.21%,54.77%, and low area of 6.2%,21.2%,31.4% for 4,8,16-bit respectively compared to BEC SQRT-CSA.