Publication Type : Conference Paper
Publisher : 2017 7th International Symposium on Embedded Computing and System Design (ISED)
Source : 2017 7th International Symposium on Embedded Computing and System Design (ISED), IEEE, Durgapur, India (2017)
Url : https://ieeexplore.ieee.org/document/8303941
Keywords : Discrete wavelet transforms Architecture Delays Memory management Hardware design languages
Campus : Bengaluru
School : School of Engineering
Center : Electronics Communication and Instrumentation Forum (ECIF)
Department : Electronics and Communication
Year : 2017
Abstract : In this work, an approach for optimizing the 3-D Discrete wavelet transform (3-D DWT) architecture is recommended. Conventional 3-D DWT architectures include basic building blocks such as 1-D DWT module, 2-D DWT module, transpose memory unit, and temporal memory unit. Proposed 3D DWT architecture is designed by suitably interconnecting the fundamental constituents (1-D DWT and 2-D DWT modules) which do not demand transposition and temporal memory units. Architecture employing the recommended approach is realized in gate level Verilog HDL. Design is functionally verified, synthesized using Cadence RC design compiler, and implemented on 90nm standard cell library. Experimental results exhibit that the proposed approach for the architecture offers significant gain in both area and power.
Cite this Research Publication : Ganapathi Hegde, Reddy, K. Srinivasa, and Dr. T. K. Ramesh, “An approach for area and power optimization of flipping 3-D discrete wavelet transform architecture”, in 2017 7th International Symposium on Embedded Computing and System Design (ISED), Durgapur, India, 2017.