Back close

A new PWM technique for symmetric and asymmetric seven level multilevel inverter topology with reduced number of DC sources

Publication Type : Journal Article

Publisher : International Journal of Applied Engineering Research, Research India Publications,

Source : International Journal of Applied Engineering Research, Research India Publications, Volume 10, Number 9, p.22299-22311 (2015)

Url : https://www.researchgate.net/publication/282275768_A_new_PWM_technique_for_symmetric_and_asymmetric_seven_level_multilevel_inverter_topology_with_reduced_number_of_DC_sources

Campus : Bengaluru

School : School of Engineering

Department : Electrical and Electronics

Year : 2015

Abstract : The Multilevel inverters are the predominating one among the emerging trends in the field of power electronics. This can be applied in many applications especially on the power quality. The topology that has been proposed in this paper presents a seven level H-Bridge inverter with a new PWM control strategies for both symmetric and asymmetric and their comparison is shown. The proposed inverter topology has two sets of units. One is cascaded H bridge section which has three sub multilevel inverters which are connected serially with H bridge multilevel inverter section. It produces the desired stepped output waveform from three DC sources. This paper mainly focuses on the Total harmonic distortion, efficiency improvement of the multilevel inverter and quality of output voltage waveform. This topology has been implemented with only seven switches to obtain seven level. Fundamental switching scheme and New PWM technique is implemented to reduce the total harmonic distortion (THD). The proposed topology is suitable for N number of levels. The proposed performance of the PWM strategy in terms of output voltage and THD is shown using MATLAP/Simulink © Research India Publications.

Cite this Research Publication : V. S. Kirthika Devi and Iyengar, S. G. Srivani, “A new PWM technique for symmetric and asymmetric seven level multilevel inverter topology with reduced number of DC sources”, International Journal of Applied Engineering Research, vol. 10, pp. 22299-22311, 2015.

Admissions Apply Now