Publication Type : Journal Article
Source : AEU-International Journal of Electronics and Communications, 2018, 97, pp. 165–177
Url : https://www.sciencedirect.com/science/article/abs/pii/S1434841117317545
Campus : Bengaluru
School : Department of Electronics and Communication Engineering
Department : Electronics and Communication
Year : 2018
Abstract : In this paper, area and power efficient lifting and flipping discrete wavelet transform (DWT) architectures are proposed. DWT architectural metrics such as critical path delay, area of utilization, power consumption are mainly dependent on the arithmetic components such as adders and multipliers. They constitute the data-path of the DWT structure. A multiplier of the DWT data-path plays major role in basic lifting, flipping cells and further it demands optimization. In this work, an area and power efficient lifting and flipping cells are implemented using look up table (LUT) based multipliers. The proposed DWT architectures are implemented in gate level Verilog HDL and are synthesized using Cadence RC design compiler. Based on the area, delay, and power results obtained from post synthesis, parameters like area delay product (ADP) and power delay product (PDP) are computed. The ADP and PDP values prove that the proposed LUT based architectures are efficient over recently projected lifting and flipping DWT architectures.
Cite this Research Publication : Hegde, G., Reddy, K.S., Shetty Ramesh, T.K., A new approach for 1-D and 2-D DWT architectures using LUT based lifting and flipping cell, AEU-International Journal of Electronics and Communications, 2018, 97, pp. 165–177