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Dr. Harish Ram D. S.

Associate Professor, Electronics and Communication Engineering, School of Engineering, Coimbatore

Qualification: M.E, Ph.D
ds_harishram@cb.amrita.edu
Ph: +91 9446944312
Dr. Harish Ram D. S's Google Scholar Profile
Research Interest: Digital System Design, Low Power VLSI Design, Very-Large-Scale Integration (VLSI) Architecture

Bio Publications EDUCATION PROFESSIONAL APPOINTMENTS Membership in Professional Bodies Teaching Research
Bio

Dr. Harish Ram D. S. currently serves as Assistant Professor at the department of Electronics and Communication Engineering, School of Engineering, Coimbatore Campus. He joined AAmrita Vishwa Vidyapeetham in 2008. His areas of research include Low Power VLSI Design, VLSI Architectures and Digital System Design.

Dr. Harish is a life member of IETE and ISTE.

 

Publications

Conference Proceedings

Year : 2020

Detection of Interference in C-Band Signals using K-Means Clustering

Cite this Research Publication : S. S. Natarajan, R. Varun, A., Shivasubramanian, G., Thamayandran, D., Dharani, M., Gandhiraj, R., Sundaram, G. A. Shanmug, Kumar, A. K. Pradeep, Binoy, N. B., Dr. T. Rajagopalan, and Ram, D. S. Harish, “Detection of Interference in C-Band Signals using K-Means Clustering”, 2020 International Conference on Communication and Signal Processing (ICCSP). 2020.

Publisher : ICCSP

Year : 2020

Evidence of Scatter in C-band Spatio-temporal Signals using Machine Learning Models

Cite this Research Publication : H. I. Surej, Karthic, S., Vigneshwara, G., Jeyashri, T., Dr. T. Rajagopalan, Gandhiraj, R., Kumar, K. A. Pradeep, Binoy, B. N., Sundaram, G. A. Shanmug, and Ram, D. S. Harish, “Evidence of Scatter in C-band Spatio-temporal Signals using Machine Learning Models”, 2020 International Conference on Communication and Signal Processing (ICCSP). 2020.

Publisher : ICCSP

Year : 2014

Hardware implementation of quasigroup based encryption

Cite this Research Publication : N. A. Nikhil and Dr. Harish Ram D. S., “Hardware implementation of quasigroup based encryption”, Proceedings of International Conference on Embedded Systems (ICES). pp. 55-58, 2014.

Publisher : Proceedings of International Conference on Embedded Systems (ICES),

Journal Article

Year : 2015

FPGA BASED SYSTEM FOR DENIAL OF SERVICE DETECTION IN SMART GRID

Cite this Research Publication : J. Balaji A. and Dr. Harish Ram D. S., “FPGA BASED SYSTEM FOR DENIAL OF SERVICE DETECTION IN SMART GRID”, ARPN Journal of Engineering and Applied Sciences, vol. 10, 2015.

Publisher : Asian Research Publishing Network

Year : 2015

A fast and scalable pattern matching scheme for NIDS using Z algorithm

Cite this Research Publication : P. Dhanesh and Dr. Harish Ram D. S., “A fast and scalable pattern matching scheme for NIDS using Z algorithm”, International Journal of Applied Engineering Research, vol. 10, pp. 37563-37568, 2015.

Publisher : Research India Publications

Year : 2013

Improved Low Power FPGA Binding of Datapaths from Data Flow Graphs with NSGA II -based Schedule Selection

Cite this Research Publication : Dr. Harish Ram D. S., Umadevi, S., and Bhuvaneswari, M. C., “Improved Low Power FPGA Binding of Datapaths from Data Flow Graphs with NSGA II -based Schedule Selection”, Advances in Electrical and Computer Engineering, vol. 13, pp. 85-92, 2013.

Publisher : Advances in Electrical and Computer Engineering,

Year : 2012

A novel framework for applying multiobjective GA and PSO based approaches for simultaneous area, delay, and power optimization in high level synthesis of datapaths

Cite this Research Publication : Dr. Harish Ram D. S., Bhuvaneswari, M. Cb, and Prabhu, S. Sa, “A novel framework for applying multiobjective GA and PSO based approaches for simultaneous area, delay, and power optimization in high level synthesis of datapaths”, VLSI Design, vol. 2012, 2012.

Publisher : VLSI Design

Book Chapter

Year : 2015

Design Space Exploration for Scheduling and Allocation in High Level Synthesis of Datapaths

Cite this Research Publication : M. C. Bhuvaneswari, Dr. Harish Ram D. S., and Neelaveni, R., “Design Space Exploration for Scheduling and Allocation in High Level Synthesis of Datapaths”, in Application of Evolutionary Algorithms for Multi-objective Optimization in VLSI and Embedded Systems, M. C. Bhuvaneswari, Ed. New Delhi: Springer India, 2015, pp. 69–92.

Publisher : Springer India

Conference Paper

Year : 2015

3-D stack of waveguide structures with hour-glass slot structure for terahertz antenna applications

Cite this Research Publication : Dr. Harish Ram D. S., Srinivasan, S., Srinikethan, M. S., and Dr. Shanmugha Sundaram G. A., “3-D stack of waveguide structures with hour-glass slot structure for terahertz antenna applications”, in 2015 International Conference on Advances in Computing, Communications and Informatics, ICACCI 2015, 2015, pp. 689-693.

Publisher : Institute of Electrical and Electronics Engineers Inc.,

Year : 2011

A novel evolutionary technique for multi-objective power, area and delay optimization in High Level Synthesis of datapaths

Cite this Research Publication : Dr. Harish Ram D. S., Bhuvaneswari, M. Cb, and Logesh, S. Ma, “A novel evolutionary technique for multi-objective power, area and delay optimization in High Level Synthesis of datapaths”, in Proceedings - 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011, Chennai, 2011, pp. 290-295.

Publisher : ISVLSI 2011

Year : 2011

Multi-objective optimization of power, area and delay during high-level synthesis of DFG’s – A genetic algorithm approach

Cite this Research Publication : S. Ma Logesh, Ram, D. S. Ha, and Bhuvaneswari, M. Cb, “Multi-objective optimization of power, area and delay during high-level synthesis of DFG's - A genetic algorithm approach”, in ICECT 2011 - 2011 3rd International Conference on Electronics Computer Technology, Kanyakumari, 2011, vol. 1, pp. 108-112.

Publisher : ICECT 2011 - 2011 3rd International Conference on Electronics Computer Technology

Year : 2011

High level synthesis of data flow graphs using integer linear programming for switching power reduction

Cite this Research Publication : A. S. Yazhini and Dr. Harish Ram D. S., “High level synthesis of data flow graphs using integer linear programming for switching power reduction”, in 2011 - International Conference on Signal Processing, Communication, Computing and Networking Technologies, ICSCCN-2011, Thuckalay, 2011, pp. 475-479.

Publisher : IEEE

EDUCATION
Qualification College  University  Year
Ph. D. PSG College of Technology Anna University, Chennai 2014
M.E. (Applied Electronics) PSG College of Technology Bharathiar University 2000
B. Tech. (ECE) NSS College of Engineering University of Calicut 1993
PROFESSIONAL APPOINTMENTS
Year Affiliation
2021 – Present Associate Professor, Department of Electronics and Communication Engineering, Amrita School of Engineering, Coimbatore.
2008 – 2021 Assistant Professor, Department of Electronics and Communication Engineering, Amrita School of Engineering, Coimbatore.
2003 – 2008 Assistant Professor (ECE), VLB Janakiammal College of Engg, Coimbatore.
2000 – 2003 Project Leader (VLSI Design), Accel Technologies, Chennai.
1994 – 1997 Senior Engineer (QA), BPL Telecom, Palakkad.
Membership in Professional Bodies
  • Life Member IETE, ISTE
Teaching
  • VLSI System Design using HDLs
  • Computer Architecture
  • VLSI Architectures for Hardware Security and Trust
  • Digital System Design
  • Low Power VLSI Design
  • Hardware Software Codesign of Digital Systems
  • FPGA Based Honeypot design
  • Machine Learning approaches for FPGA accelerated malware analysis
Research

Areas of Interest

TAG Group: VLSI – Computing, Hardware Systems and Architectures

  • Architectures for security and trust in cyber physical systems
  • Unconventional computing
  • Energy efficient Design

Research Projects

  • Architectures for data integrity assurance in smart metering systems
  • Application of Machine Learning for security in Cyber Physical Systems
  • FPGA based malware detection for high speed networks (under IBM Shared University Research (SUR) Program)

Research Expertise

  • Ongoing PhD works : Data Integrity in Cyber Physical Systems, Mr A Jayanth Balaji

Projects

PG Projects

  • FPGA Based Honeypot design
  • Machine Learning approaches for FPGA accelerated malware analysis.

Funded Projects

  • Malware Detection using FPGA, Sandboxing and Machine Learning funded by IBM for $ 12000 (jointly with Centre for Cyber Security and Dept of CSE)
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